v2.0.1

Updates to HDK, SDK, and Vitis documentation. Added check for XRT install to enable Vitis hardware emulation. XRT install can now be performed automatically by running a command presented during vitis_setup.sh.

Second-Generation FPGA-Powered Amazon EC2 instances (F2)

Amazon EC2 F2 instance General Availability
F2 Instances offer customizable hardware acceleration with field programmable gate arrays (FPGAs). F2 instances are powered by up to 8 AMD Virtex UltraScale+ HBM VU47P FPGAs and are the first FPGA-based instances to feature 16GB of high-bandwidth memory. They feature a 3rd generation AMD EPYC (Milan) processor with 3x processor cores (192 vCPU), 4x networking bandwidth (100 Gbps), 2x system memory (2 TiB), and 2x NVMe SSD (7.6 TiB), compared to F1 instances.

https://aws.amazon.com/blogs/aws/now-available-second-generation-fpga-powered-amazon-ec2-instances-f2/
https://aws.amazon.com/ec2/instance-types/f2/

Migration between F1 and U200 in vivado flow is now supported

This release includes updates to the documentation and references for migration between F1 and U200 in vivado flow. The migration between F1 and U200 is now fully supported. Please refer to the FPGA developer kit v1.4.24 for support.

Release v1.4.23

FPGA developer kit now supports Xilinx Vitis/Vivado 2021.2

We recommend developers upgrade to 2021.2 to benefit from the new features, bug fixes, and optimizations. To upgrade your developer kit, make sure you use the FPGA Developer AMI v1.12.0 and simply update to the latest FPGA developer kit v1.4.23.

New features

• FPGA developer kit now supports Xilinx Vivado/Vitis 2021.2
• Updated the Vitis F1 Platform to fix an issue that could cause hangs

Note:
Currently cl_uram_example fails with 2021.2 release and we are investigating the cause of failure

Release v1.4.22

FPGA developer kit now supports Jumbo frames in the Virtual Ethernet framework for Amazon EC2 F1 instances

With this release we are announcing support for jumbo frames in virtual ethernet framework in the AWS FPGA Developer kit. Developers using Amazon EC2 F1 instances can now use jumbo frames to get the maximum allowed networking bandwidth for the instance, delivering up to double the virtual ethernet networking performance.

Xilinx tool 2017.4 EOL timeline announced

We've announced the deprecation of Xilinx tools 2017.4. Follow the announcement in detail on our forum

Changelog

• Virtual Ethernet upgraded to support Jumbo Frames.
  • Update dpdk to v20.02 for virtual eth instance and dpdk to v20.08 and pktgen to v20.09 for pktgen instance
• Updated the end of life announcement table
  Xilinx 2017.4 EOL timeline announced.
• Updated docs to not include folder creation in s3 mb api call by @deeppat in #531
• Fix IPI build script and Pythonpath bugs by @deeppat in #535
• Ensure udev rules works if devices changed since creation by @xlz-jgoutin in #533
• Add option to allow "others" instead of "group" in udev rules by @xlz-jgoutin in #534
• Doc updates and test fixes by @deeppat in #538
• XDMA.ko build fixed for kernel version used on Ubuntu 20.04 by @jelicicm in #536

New Contributors

• @xlz-jgoutin made their first contribution in #533
• @jelicicm made their first contribution in #536

Full Changelog: v1.4.21...v1.4.22

Release v1.4.21

FPGA developer kit now supports Xilinx Vitis/Vivado 2021.1

We recommend developers upgrade to 2021.1 to benefit from the new features, bug fixes, and optimizations. To upgrade your developer kit, make sure you use the FPGA Developer AMI v1.11.0 and simply update to the latest FPGA developer kit v1.4.21.

New features

• FPGA developer kit now supports Xilinx Vivado/Vitis 2021.1

Release v1.4.15b

Updated Vivado version allow list to include AR73068 with older versions

v1.4.20

Release v1.4.20

• Bug Fix release to fix XDMA to fix Issue #516
• Miscellaneous documentation updates

Release v1.4.19

Bug Fix Release

We have identified a bug in the flop_ccf.sv module that can potentially impact timing closure of designs.
The module is instantiated in sh_ddr.sv and inadvertently introduces a timing path on the reset logic.
Although there is no functional impact, it may increase Vivado tool’s effort in timing closure of design.
There should be no functional impact from this bug if your design has already met timing.

Please check ERRATA for more info.

Release v1.4.18

FPGA developer kit now supports Xilinx Vitis/Vivado 2020.2

We recommend developers upgrade to 2020.2 to benefit from the new features, bug fixes, and optimizations. To upgrade your developer kit, make sure you use the FPGA Developer AMI v1.10.0 and simply update to the latest FPGA developer kit v1.4.18.

New features

• FPGA developer kit now supports Xilinx Vivado/Vitis 2020.2