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Do not encode safe points with -1 offset. #110845
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/azp run runtime-coreclr gcstress-extra, runtime-coreclr gcstress0x3-gcstress0xc |
Azure Pipelines successfully started running 2 pipeline(s). |
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I think this is ready for review. CC: @dotnet/jit-contrib This is really a rebased change as in #104336 (which was approved, but then uncovered stress/JIT issues). The issues were eventually fixed separately from the whole PR, but by that time it was too close to 9.0 shipping and the actual change did not make it. So here it is. |
NB: The change to GCInfo semantics is compat breaking and this PR cannot be merged as-is. We will the min R2R version to be incremented. @jkotas - I wonder if this, together with removal of Alternatively, we can keep this around ready and wait for something else to force minversion change. Usually some kind of new JIT helper forces that eventually. |
The change now includes not recording Return Kind (follow up to #110799) and bumps up the default GCInfo version as well as min major R2R version. |
======== Size impact of this change on arm64: Before the change: After the change: executable size reduction is roughly 179Kb ( ~0.8% ) The reduction in size is not the primary goal (simplifying the invariants is), but it is nice that the size went down as a sideeffect. We see a larger diff here, compared to #104336 because of additional effects of not recording Return Kind, which also allows more methods to use slim GC Info format. |
/azp run runtime-coreclr gcstress-extra, runtime-coreclr gcstress0x3-gcstress0xc |
Azure Pipelines successfully started running 2 pipeline(s). |
@mikem8361 @tommcdon - this change has effect on GC Info encoding and when merged may need adjustments in diagnostics repo. |
src/coreclr/gcinfo/gcinfoencoder.cpp
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@@ -776,12 +774,14 @@ void GcInfoEncoder::SetReversePInvokeFrameSlot(INT32 spOffset) | |||
m_ReversePInvokeFrameSlot = spOffset; | |||
} | |||
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#ifndef TARGET_X86 | |||
void GcInfoEncoder::SetReturnKind(ReturnKind returnKind) |
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This is only used on Linux x86. Is there something fundamental that prevents Linux x86 to be switched to the same plan as the other GC encoder platforms? It would make the change simpler.
I know that there is no testing for Linux x86. I would not be worried about it. Since there is no testing, Linux x86 is likely broken anyway.
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Hmm. I actually wanted to make this "ifdef", not "ifndef". How does this even pass tests?
x86 GC info is not supposed to be changed.
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Ah. This is still the non-x86 GC encoder. The confusion was because this is a part where non-x86 encoder had an ifdef for TARGET_X86
, so I assumed it is a shared path between two encoders.
It is not. The reason for original ifdef was just because X86 would have a different default state for the return kind.
Regardless x86 or not, m_ReturnKind
is not going to be used by the non-legacy GC encoder. The non-legacy GC info is expressive enough to not require encoding return registers in an additional/special way.
This does not need to be ifdef'd. It should be removed. There is indeed nothing special about X86 here.
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I think my lack of knowledge about GC encoder history shows here.
/azp run runtime-coreclr gcstress-extra, runtime-coreclr gcstress0x3-gcstress0xc |
Azure Pipelines successfully started running 2 pipeline(s). |
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Nice simplification!
Thanks!! |
Same as #104336,
except for JIT fixes that were included in 9.0 as a part of #105596
When the code position after a call site is a safe point, its GC info is now applicable regardless of how instruction pointer has arrived at this position - by executing a call (and unwinding), returning from a call or jumping around the call,...
This invariant holds in both fully and partially interruptible code.
Therefore leaf/nonleaf/faulted-in-partial/faulted-in-interruptible scenarios all can work the same and we no longer need to resort to various disambiguation schemes.
In particular we do not need to pre-adjust safe point positions in partially interruptible code by
-1
, into the middle of a previous instruction, and then carefully compensate for that in bunch of places.An additional benefit is that code offsets in GC info are now all instruction-aligned, thus on RISC architectures fewer bits could be used to encode those.
Fixes: #5677
X86: the change does not affect the legacy X86 GC info