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Optional Tracing #26

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Optional Tracing #26

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cc0602f
Changed the ibexc_top_tracing ports to match ibexc_top
HU90m Mar 13, 2024
beb71aa
Allow RVFI to be unset
HU90m Mar 13, 2024
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3 changes: 0 additions & 3 deletions ibex_top_tracing.core
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Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,6 @@ parameters:
RVFI:
datatype: bool
paramtype: vlogdefine
default: true

SYNTHESIS:
datatype: bool
Expand Down Expand Up @@ -111,8 +110,6 @@ targets:
default: &default_target
filesets:
- files_rtl
parameters:
- RVFI=true
toplevel: ibex_top_tracing

lint:
Expand Down
29 changes: 17 additions & 12 deletions rtl/ibexc_top_tracing.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,10 @@
module ibex_top_tracing import ibex_pkg::*; import cheri_pkg::*; #(
parameter int unsigned DmHaltAddr = 32'h1A110800,
parameter int unsigned DmExceptionAddr = 32'h1A110808,
parameter bit DbgTriggerEn = 1'b1,
parameter int unsigned DbgHwBreakNum = 2,
parameter int unsigned MHPMCounterNum = 0,
parameter rv32b_e RV32B = RV32BNone,
parameter int unsigned HeapBase = 32'h2001_0000,
parameter int unsigned TSMapBase = 32'h2004_0000, // 4kB default
parameter int unsigned TSMapSize = 1024, // in words
Expand All @@ -25,7 +29,6 @@ module ibex_top_tracing import ibex_pkg::*; import cheri_pkg::*; #(
input logic rst_ni,

input logic test_en_i, // enable all clock gates for testing
input logic scan_rst_ni,
input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_i,

input logic cheri_pmode_i,
Expand Down Expand Up @@ -60,7 +63,6 @@ module ibex_top_tracing import ibex_pkg::*; import cheri_pkg::*; #(
output logic tsmap_cs_o,
output logic [15:0] tsmap_addr_o,
input logic [31:0] tsmap_rdata_i,
input logic [6:0] tsmap_rdata_intg_i, // not used in ibexc_top
input logic [MMRegDinW-1:0] mmreg_corein_i,
output logic [MMRegDoutW-1:0] mmreg_coreout_o,
output logic cheri_fatal_err_o,
Expand All @@ -85,10 +87,16 @@ module ibex_top_tracing import ibex_pkg::*; import cheri_pkg::*; #(

// CPU Control Signals
input fetch_enable_t fetch_enable_i,
output logic core_sleep_o
);
output logic core_sleep_o,
output logic alert_minor_o,
output logic alert_major_internal_o,
output logic alert_major_bus_o,

// DFT bypass controls
input logic scan_rst_ni
);

`ifdef RVFI
logic rvfi_valid;
logic [63:0] rvfi_order;
logic [31:0] rvfi_insn;
Expand Down Expand Up @@ -134,16 +142,17 @@ module ibex_top_tracing import ibex_pkg::*; import cheri_pkg::*; #(
assign unused_rvfi_ext_nmi = rvfi_ext_nmi;
assign unused_rvfi_ext_debug_req = rvfi_ext_debug_req;
assign unused_rvfi_ext_mcycle = rvfi_ext_mcycle;
`endif

ibex_top #(
.DmHaltAddr (DmHaltAddr ),
.DmExceptionAddr (DmExceptionAddr ),
.MHPMCounterNum (13 ),
.MHPMCounterNum (MHPMCounterNum),
.MHPMCounterWidth (40),
.DbgTriggerEn (1'b1),
.DbgHwBreakNum (4),
.DbgTriggerEn (DbgTriggerEn),
.DbgHwBreakNum (DbgHwBreakNum ),
.RV32E (1'b0),
.RV32B (RV32BFull),
.RV32B (RV32B),
.WritebackStage (1'b1),
.BranchPredictor (1'b0),
.CHERIoTEn (1'b1),
Expand Down Expand Up @@ -257,10 +266,6 @@ module ibex_top_tracing import ibex_pkg::*; import cheri_pkg::*; #(

// ibex_tracer relies on the signals from the RISC-V Formal Interface
// synthesis translate_off
`ifndef RVFI
$fatal("Fatal error: RVFI needs to be defined globally.");
`endif

`ifdef RVFI
ibex_tracer #(
.DataWidth (DataWidth)
Expand Down